Circuit and method for multi-phase alignment

ABSTRACT

A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of U.S. Provisional ApplicationNo. 60/223,112 filed Aug. 3, 2000 and, U.S. Provisional Application No.60/224,169 filed Aug. 9, 2000 both of which are incorporated byreference herein in their entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to high speed sampling circuits. Moreparticularly, the invention relates to a circuit and method for reducingsampling distortion.

[0004] 2. Background Art

[0005] A sample and hold circuit periodically captures the amplitude ofa variable analog signal. In many sample and hold circuits, distortionis produced by circuit components that limit the useful voltage range ofan input signal or limit the useful frequency of the input signal.Distortion may be produced, for example, by nonlinear resistancecharacteristics of switches in the sample and hold circuits that arecaused by effects such as field effect transistor (FET) thresholdturnoff, bulk effect, or manufacturing variations. Distortion may alsobe produced by parasitic capacitances of switches in the sample and holdcircuit, nonlinear load currents in the input source resistance that arecaused by semiconductor junctions of switches in the sample and holdcircuits, and terminal resistance of switches in the sample and holdcircuits.

[0006] These distortions are generally nonlinear functions of theapplied input voltage. In a sampling circuit, the applied input voltageis the signal to be sampled. This type of sampling is called signaldependent sampling. In applications requiring low distortion and highsample fidelity, signal dependent sampling is undesirable.

[0007] Various methods are used to eliminate the distortion caused bysignal dependent sampling. These methods include active cancellationcircuitry, multiple sample circuits, and other distortion cancellationmethods requiring additional complex and expensive circuit components.In one method, an auxiliary sampling circuit is added to producecanceling distortion that is proportionally larger with respect to thesampled signal than the distortion produced in the main samplingcircuit.

[0008] A simple and inexpensive method of eliminating signal dependentsampling distortion is to isolate the sample hold device from thedistortion causing events. This method locks the sample value in thehold device before opening the sampling switch and initiating thedistortion causing event. This method is simple to implement andrequires only minor hardware changes. However, there are limitations inthe sample and hold control circuitry that prohibit its use at highsampling rates.

[0009] What is needed is a circuit and method for eliminatingdistortion, caused by signal dependant sampling, that does not requirecomplex or expensive circuitry and is suitable for use in high speedsampling applications.

BRIEF SUMMARY OF THE INVENTION

[0010] The invention comprises a circuit and method for aligning pulseedges used to control a sample and hold circuit. The multi-phasealignment circuit comprises an edge discriminator connected to a firstsummer, a second summer, and a rate adjuster. The second summer is alsoconnected to the rate adjuster. The edge discriminator receives a clocksignal and separates the clock signal into rising and falling edges. Therate adjuster adjusts the slope of one of the falling edges to a desiredvalue. The rising edges and the falling edges are summed in the firstsummer and output as a clock signal. The rising edges and the adjustedfalling edges are summed in the second summer and output as an adjustedclock signal. The rising edges of the clock signal and the adjustedclock signal are aligned. The clock signal and adjusted clock signalcontrol a high speed sample and hold circuit.

BRIEF DESCRIPTION OF THE FIGURES

[0011] The present invention is described with reference to theaccompanying drawings. In the drawings, like reference numbers indicateidentical or functionally similar elements. Additionally, the leftmostdigit(s) of a reference number identifies the drawing in which thereference number first appears.

[0012]FIG. 1 illustrates a sample and hold circuit.

[0013]FIG. 2 illustrates the operating characteristics of asemiconductor switch.

[0014]FIG. 3 illustrates an improved sample and hold circuit.

[0015]FIG. 4A illustrates a circuit for generating control signals.

[0016]FIG. 4B illustrates details of control signal waveforms.

[0017]FIG. 5A illustrates an improved circuit for generating controlsignals.

[0018]FIG. 5B illustrates an alternate embodiment of the control signalgenerator.

[0019]FIG. 6 illustrates details of improved control signal waveforms.

[0020]FIG. 7 illustrates details of a multi-phase alignment circuit.

[0021]FIG. 8 illustrates steps of a method for generating multi-phasecontrol signals.

[0022]FIG. 9 illustrates details of a method step for adjusting afalling edge slope.

DETAILED DESCRIPTION OF THE INVENTION

[0023] I. Example Circuit Application

[0024] Before describing the invention in detail, it is useful todescribe an example of a sampling circuit containing the invention. Themulti-phase alignment circuit invention is not limited to the samplingcircuit that is described herein. The multi-phase alignment circuitinvention is applicable to other sampling and non-sampling applicationsas will be understood to those skilled in the relevant arts based on thediscussions given herein.

[0025]FIG. 1 illustrates a sample and hold circuit 100. The sample andhold circuit 100 comprises an input 115, a sample switch 120, a holdcapacitor 125, an output switch 130, an output 160, an output groundswitch 140, a sample ground switch 150, a sample control line 165, anoutput control line 170 and a ground 135. The sample switch 120 and thesample ground switch 150 are open and closed by a sample control signal175 on the sample control line 165. The output switch 130 and the outputground switch 140 are open and closed by an output control signal 180 onthe output control line 170.

[0026] The sample and hold cycle begins when the output control signal180 opens the output switch 130 and the output ground switch 140. Thesample control signal 175 closes the sample switch 120 and the sampleground switch 150. A sampled signal 110 charges the hold capacitor 125to a voltage representative of the sampled signal 110. The samplecontrol signal 175 opens the sample switch 120 and sample switch ground150 isolating the hold capacitor 125 from the sampled signal 110. Theoutput control signal 180 closes the output switch 130 and the outputground switch 140, applying the voltage on the hold capacitor 125 to theoutput 160. The voltage at the output 160 is representative of thesampled signal 110 at the sample time. An external circuit dischargesthe hold capacitor 125 and the sample and hold cycle is complete.

[0027] In an embodiment of the sample and hold circuit 100, the sampleswitch 120, the output switch 130, the output ground switch 140, and thesample ground switch 150 are field effect transistors (FETs). Each FETcomprises a gate, a source, and a drain. The sample control line 165 iscoupled to the sample switch 120 gate and the sample ground switch 150gate. The output control line 170 is coupled to the output switch 130gate and the output ground switch 140 gate. The sample switch 120 sourceis coupled to the input 115. The sample control signal 175 causes thesample switch 120 and the sample ground switch 150 to open and closed byapplying a desired voltage to the sample switch 120 gate and the sampleground switch 150 gate. The output control signal 180 causes the outputswitch 130 and the output ground switch 140 to open and closed byapplying a desired voltage to the output switch 130 gate and the outputground switch 140 gate.

[0028] The sampled signal 110 is applied to the input 115 and the sampleswitch 120 source. A time varying sampled signal 110 causes a timevarying voltage at the sample switch 120 source.

[0029]FIG. 2 illustrates a characteristic curve 210 of a field effecttransistor biased to operate as the sampling switch 120. The voltagemeasured between the sample switch 120 gate and the sample switch 120source is a V_(GS) 205. Referring to FIG. 2, the sampled input 110 issuperimposed on a characteristic curve 210 to illustrate the effect ofvarying the V_(gs) 205 on the sample switch 120. With the voltage at thesample switch 120 gate constant, the V_(gs) 205 varies between a V₁ 220and a V₃ 240 according to the instantaneous magnitude of the sampledsignal 110.

[0030] The sample switch 120 is biased to open when V_(gs) 205 is equalto V_(o) 230. The condition for V_(GS) 205=V_(o) 230 depends on the sumof the sampled signal 110 and the sample control signal 175. The sampleswitch 120 could open before, or after the sample control signal 175reaches the V_(o) 230. The variation in the sample switch 120 openingtimes causes a sample signal dependent variation in the voltage on thehold capacitor 125 and thus a signal dependent distortion in the sampledvalue. In addition, if the input signal 110 is large enough, the sampleswitch 120 could still be closed when the output control signal 180closes the output ground switch 140, grounding the input signal 110. Thesignal and timing distortion caused by signal dependent sampling isundesirable.

[0031]FIG. 3 illustrates a modified sample and hold circuit 300. Themodified sample and hold circuit 300 comprises the sample and holdcircuit 100, a sample ground control line 310, and a sample groundcontrol signal 320. The sample control line 165 is uncoupled from thesample ground switch 150. A sample ground control signal 320 is coupledto the sample ground switch 150 through the sample ground control line310.

[0032] The modified sample and hold circuit 300 eliminates signaldependent sampling by opening the sample ground switch 150 just prior toopening the sample switch 120.

[0033] Referring to FIG. 3, the sample and hold cycle begins when theoutput control signal 180 opens the output switch 130 and the outputground switch 140. The sample control signal 175 closes the sampleswitch 120 and simultaneously, the sample ground control signal 320closes the sample ground switch 150. The sampled signal 110 charges thehold capacitor 125 to a voltage representative of the sampled signal110. The sample ground control signal 320 opens the sample ground switch150, isolating the hold capacitor 125 from the ground 135. The samplecontrol signal 175 opens the sample switch 120. The output controlsignal 180 closes the output switch 130 and the output ground switch140, applying voltage on the hold capacitor 125 to the output 160. Thevoltage at output 160 is representative of the sample taken. An externalcircuit discharges the hold capacitor 125 and the sample and hold cycleis complete.

[0034] When the sample ground switch 150 is opened the hold capacitor125 is placed in an open circuit condition. The quantity of charge onthe hold capacitor 125 is fixed and unaffected by distortions associatedwith opening the sample switch 120. The sample ground switch 150 is notaffected by the input signal 110, therefore the sample distortion causedby isolating the hold capacitor 125 with the sample switch 120 iseliminated and signal dependent sampling is prevented.

[0035] II. Generating the Switch Control Signals

[0036]FIG. 4A illustrates a control signal generator 400 for producingcontrol signals for modified sample and hold circuit 300. The controlsignal generator 400 is presented to highlight the differences betweenthe present invention and an existing method of generating controlsignals with specific pulse edge alignments.

[0037] The control signal generator 400 comprises an input 401 coupledto a first delay 440 and a first AND gate 430. The first delay 440 iscoupled to the first AND gate 430. A second delay 445 is coupled betweenthe input 401 and a second AND gate 435.

[0038] An input clock signal 460 is applied to the input 401. The inputclock signal 460 is delayed a T_(D) 476 by the first delay 440 and isoutput as a delayed clock signal 407 a. The input clock signal 460 andthe delayed clock signal 407 a are logical AND'ed in the first AND gate430 and output as an adjusted clock signal 423. The input clock signal460 is delayed T_(D) 476 by the second delay 445 to create a delayedclock signal 407 b. The delayed clock signal 407 b is logical AND'edwith the delayed clock signal 407 b in the second AND gate 435 andoutput as a clock signal 424.

[0039] The clock signal 424 is coupled to the sample control line 165and the adjusted clock signal 423 is coupled to the sample groundcontrol line 310. These connections allow the control signal generator400 to control the modified sample and hold circuit 300. The sampleswitch 120 is closed by a positive transition on the sample control line165. The sample ground switch 150 is closed by a positive transition onthe sample ground control line 310. The sample switch 120 is opened by anegative transition on the sample control line 165. The sample groundswitch 150 is opened by a negative transition on the sample groundcontrol line 310.

[0040]FIG. 4B illustrates timing details between the input clock signal460, the delayed signal 407, the adjusted clock signal 423, and theclock signal 424.

[0041] The input clock signal 460 is generated by an external circuitand coupled to the input 401. Methods for generating clock signals arewell known and one of skill in the art will understand how to generatethe input clock signal 460. The input clock signal 460 comprises arising edge 471 and a falling edge 474. The delayed clock signal 407comprises a rising edge 471 a and a falling edge 474 a. The adjustedclock signal 423 comprises an adjusted clock rising edge 471 b and anadjusted clock falling edge 474 b. The clock signal 424 comprises aclock rising edge 471 c and a clock falling edge 474 c.

[0042] The delayed clock signal 407 is input clock signal 460 delayed byT_(D) 476. The adjusted clock signal 423 is delayed clock signal 407 alogical AND'ed with input clock signal 460. The clock signal 424 isdelayed clock signal 407 b logical AND'ed with the delayed clock signal407 b.

[0043] To open the sample ground switch 150 before the sample switch120, the adjusted clock falling edge 474 b must occur before the clockfalling edge 474 c. The adjusted clock falling edge 474 b and the clocksignal falling edge 474 c are staggered by TD 476. The adjusted clocksignal rising edge 471 b and the clock signal rising edge 471 c are eachdelayed from input clock signal 460 by TD 476.

[0044] The clock signal 424 and the adjusted clock signal 423 must bealigned to provide an adequate period for electrical transients toattenuate. This period is known as circuit settling. If the circuitsettling time is inadequate, transients generated in one sample cyclecould be present in subsequent cycles. Unsettled transients areunpredictable and undesirable. As the sampling rate is increased, sampleperiod decreases. Finding adequate time for circuit settling becomes anupper limit to further increasing the sampling rate. Any portion of theclock period recovered from inefficient use can be applied to circuitsettling time while increasing the sampling rate.

[0045] In one embodiment, the multi-phase alignment circuit will operatewith an eight-nanosecond sample period. At that sampling rate thecircuit settling time is four nanoseconds. That allows four nanosecondsfor the clock signal 424 and the adjusted clock signal 423 to transitionhigh, the sample switch 120 and the sample ground switch 150 to close,the adjusted clock signal 423 to transition low, the sample groundswitch 150 to open, clock signal 424 to transition low, and the sampleswitch 120 to open.

[0046] To maximize the available settling time within a given clockperiod, the clock rising edge 471 c and the adjusted clock rising edge471 b must be aligned to transition high, closing the sampling switch120 and the second sampling switch 150 simultaneously. Misalignmentbetween the clock rising edge 471 c and the adjusted clock rising edge471 b delays the start of the settling period. The interval betweenT_(R) 477 and T_(FE) 478 defines the clock period available for circuitsettling. If the clock rising edge 471 c occurs before the adjustedclock rising edge 471 b, the settling time is reduced. If the adjustedclock rising edge 471 b occurs before the adjusted clock rising edge 471c, the settling time will also be reduced. To ensure alignment TD 476 inthe first delay 440 must equal TD 476 in the second delay 445. Anydifference staggers the clock rising edge 471 c and the adjusted clockrising edge 471 b.

[0047] The alignment of the clock falling edge 474 c and the adjustedclock falling edge 474 b also affects circuit settling time. Thedifference between T_(FE) 478 and T_(F) 479 is TD 476. If the clockrising edge 471 c and the adjusted clock rising edge 471 b are alignedat T_(R) 477 then the circuit settling time equals (T_(F) 479 minusT_(R) 477) minus T_(D) 476. The maximum circuit settling interval occurswhen T_(D) 476 is at its minimum.

[0048] Time delays are implemented in integrated circuits using simpledevices or elements coupled in series. The total delay is the sum of theindividual elements. The total delay=T_(D) 476. A simple semiconductorinverter has an inherent signal delay of about one nanosecond. Incircuits where T_(D) 476 is many nanoseconds, many delay elements can beused and T_(D) 476>>a single element delay. Increasing or decreasingT_(D) 476 is accomplished by adding or removing elements. However, assampling rate increases, T_(D) 476 is reduced to maintain circuitsettling time. Eventually, T_(D) 476 will be equal to the delay insertedby one element. In circuits using delayed control signals, the delayinserted by one device is the minimum T_(D) 476 and therefore determinesthe maximum sample rate for a fixed settling time. In high speedsampling, a single inverter sets T_(D) 476≅one nanosecond, which usestwenty-five percent of the available clock period.

[0049] If the first delay 440 and the second delay 445 do not have anidentical T_(D) 476, the rising edges will be staggered. The staggerededges cause the sample switch 120 and the sample ground switch 150 toclose sequentially. The delay between the first switch closing and thesecond switch closing uses clock period and does not count as settlingtime.

[0050] A multi-phase clock generator is needed to overcomes thedisadvantages of delay based clock generators.

[0051] II. The Multi-Phase Alignment Circuit

[0052]FIG. 5A illustrates a multi-phase alignment circuit 500. Themulti-phase alignment circuit 500 comprises an edge discriminator 510coupled to an input 401, a rise output 511, and a fall output 512. Therise output 511 is coupled to a first summer 540 and a second summer545. The fall output 512 is coupled to the first summer 540 and a rateadjust 522. The rate adjust 522 is coupled to the second summer 545.First summer 540 is coupled to a clock output terminal 560 and secondsummer 545 is coupled to an adjusted clock output terminal 570.

[0053] The edge discriminator 510 responds to a rising edge 471 on theinput clock 460 by generating a rising edge signal 471 a at the riseoutput 511. The start, slope, and duration of the rising edge signal 471a is proportional to the rising edge 471. When the rising edge 471 ends,the rising edge signal 471 a remains a constant positive value. When afalling edge 474 of the input clock 460 is detected, the rising edgesignal 471 a is not generated. The rising edge signal 471 a is alignedwith the rinsing edge 471

[0054] The edge discriminator 510 responds to the falling edge 474 bygenerating a falling edge signal 474 a at the fall output 512. Thestart, slope, and duration of the falling edge signal 474 a isproportional to the falling edge 474. When the falling edge 474 ends,the falling edge signal 474 a remains at a zero reference value. Whenthe rising edge 471 is detected, the falling edge signal 474 a is notgenerated. The falling edge signal 474 a is aligned with the fallingedge 474.

[0055] Referring to FIG. 5A, the rising edge signal 471 a is dividedinto a rising edge signal 471 b and arising edge signal 471 c. Therinsing edge 471 b is coupled into the first summer 540 and the risingedge signal 471 c is coupled into the second summer 545. The fallingedge signal 474 a is also divided into a falling edge signal 474 b and afalling edge signal 474 c. The falling edge 474 b is coupled to thefirst summer 540 and the falling edge signal 474 c is coupled to therate adjust 522.

[0056] The rate adjust 522 responds to the falling edge signal 474 c bygenerating an adjusted falling edge signal 550 with the same initialamplitude but a greater slope than the falling edge signal 474 c. Theadjusted falling edge signal 550 reaches the zero reference value beforethe falling edge signal 474 a.

[0057] The first summer 540 functions to combine the rising edge signal471 b and the falling edge signal 474 b into a clock signal 524. Thesecond summer 545 functions to combine the rising edge signal 471 c andthe adjusted falling edge signal 550 into an adjusted clock signal 523.The clock signal 524 is aligned with the input clock 460. The adjustedclock signal 523 is aligned to the rising edge 471 but is offset at theend of the adjusted falling edge signal 550 by an interval proportionalto the difference in the slope of the falling edge 474 b and theadjusted falling edge 550.

[0058]FIG. 5B illustrates an alternate multi-phase alignment circuit501. The alternate multi-phase alignment circuit 501 comprises themulti-phase alignment circuit 500 and a rate adjust 522 b coupledbetween the rise output 511 and the first summer 540. The rate adjust522 b sets the slope of the rising edge signal 471 b and outputs anadjusted rising edge signal 551. The first summer 540 sums the fallingedge signal 474 b and the adjusted rising edge signal 551 to output asecond adjusted clock signal 526. In a manner analogous to the adjustedfalling edge signal 550, the adjusted rising edge signal 551 provides anadjustable offset between the rising edge signal 471 c in the adjustedclock signal 523 and the adjusted rising edge signal 551 in the secondadjusted clock signal 526.

[0059]FIG. 6 illustrates the clock signal 524 and the adjusted clocksignal 523. The clock signals edge transitions are exaggerated toillustrate timing details.

[0060] The clock signal 524 comprises a clock rising edge 680 and aclock falling edge 682. The adjusted clock signal 523 comprises amadjusted clock rising edge 681 and an adjusted clock falling edge 683.The clock signal 524 is coupled to the sample switch control line 165and controls when the sample switch 120 opens and closes. The adjustedclock signal 523 is coupled to the sample ground control line 310 andcontrols when the sample ground switch 150 opens and closes.

[0061] The rate adjust 522 sets the slope of the adjusted falling edge683. The start of the falling edge signal 474 b is aligned with theadjusted falling edge signal 550. The rate adjust 522 affects only theslope of the adjusted falling edge signal 550. The adjusted falling edgesignal 550 and the falling edge signal 474 b begin at a time T₃ 645. Theadjusted falling edge signal 550 ends at a T₄ 650 The falling edgesignal 474 b ends at a T₅ 655.

[0062] The sample switch 120 closes at a T_(c) 656. T_(c) 656 occurswhen the clock signal 524 is rising and midway between the minimum andmaximum clock signal 524 amplitude. The sample switch 120 opens, at aT_(O) 665, when the clock signal 524 is falling and midway between themaximum and minimum clock signal 524 amplitude. The sample ground switch150 closes at the T_(C) 656. The sample ground switch 150 opens, at aT_(FO) 660. T_(FO) 660 is the time when adjusted clock signal 523 isfalling and midway between the maximum and minimum adjusted clock signal523 amplitude. A Δt 675 is the difference between T_(FO) 660 and T_(O)665. Adjusting the slope of the adjusted clock falling edge 683 controlsthe magnitude of the Δt 675.

[0063] The multi-phase alignment circuit has several advantages.

[0064] First, the multi-phase clock circuit does not use delay devicesto vary the Δt 675. This eliminates the disadvantages of using delayelements discussed with reference to the control signal generator 300.When the adjusted clock falling edge 683 slope is set equal to the clockfalling edge 682 the Δt is zero. The multi-phase alignment circuit 500enables clock edge alignments between zero and a desired delay. Themaximum delay is limited only by the ability of circuit elementsembodying the invention to increase the slope of adjusted falling edgesignal 550.

[0065] Second, the multi-phase alignment circuit 500 recovers the clockperiod equal to the difference between T_(D) 476 and Δt 675.

[0066]FIG. 7 is a multi-phase alignment circuit 700. The multi-phasealignment circuit 700 comprises the input 401 coupled to a first gate711, a second gate 721, a third gate 753, a fourth gate 761, and a fifthgate 781. A first source 713 is coupled to a first drain 712, a firsttransistor 710, and the first gate 711. A second source 724 is coupledto a second drain 723, a second transistor 720, and the second gate 721.A third source 752 is coupled to the third gate 753, a third transistor750 and a third drain 751. A fourth source 762 is coupled to the fourthgate 761, a fourth transistor 760, and a fourth drain 763. A fifthsource 783 is coupled to the fifth gate 781, a fifth transistor 779, anda fifth drain 782. A sixth source 773 is coupled to a sixth gate 772, asixth transistor 770, and a sixth drain 771 A seventh source 742 iscoupled to a seventh gate 741, a seventh transistor 740, and a seventhdrain 743. An eighth source 733 is coupled to an eighth gate 731, aneighth transistor 730, and an eighth drain 732.

[0067] The sixth transistor 770, the seventh transistor 740, and theeighth transistor 730 function as load devices. The fifth transistor779, sixth transistor 770, seventh transistor 740, and the eighthtransistor 730 are selected to have identical impedance characteristics.When the first transistor 710 and the third transistor 750 areconducting, the impedance at the first drain 712 and the third drain 751must be equal for the rising edge 471 to have the same slope in theclock signal 524 and the adjusted clock signal 523.

[0068] When the second transistor 720, the fourth transistor 760 and thefifth transistor 779 are conducting, the impedance at the second drain723, the fourth drain 763, and the fifth drain 782 must be equal for theadditional current from the fifth transistor 779 to set the differencebetween the slope of the clock falling edge 682 and the slope of theadjusted clock falling edge 683.

[0069] A voltage supply 701 is coupled to the first source 713, thethird source 752, the sixth source 773, the sixth gate 772, the eighthsource 733, and the eighth gate 731.

[0070] A ground 702 is coupled to the second source 724, the fourthsource 762, the fifth source 783, the seventh gate 741, and the seventhsource 742.

[0071] A first summer 790 is coupled to the first drain 712, the seconddrain 723, the seventh drain 743, the eighth drain 732.

[0072] A second summer 791 is coupled to the third drain 751, the fourthdrain 763, the fifth drain 782, the sixth drain 771. As shown in FIG. 7,the summer 790 and 791 can be nodes that sum currents from theappropriate transistors.

[0073] A first capacitive load 792 is coupled between the first summer790 and the ground 702. A second capacitor 793 is coupled between thesecond summer 791 and the ground 702. The first capacitive load 792 andthe second capacitive load 793 are not a required circuit element andare shown only to visualize the inherent device capacitances. Althoughnot required, alternate embodiments could add capacitance to balanceunmatched semiconductor devices or provide a more precise means of slopecontrol than adding additional transistors.

[0074] The first device capacitance 792 is a lumped elementrepresentation of the gate-source, gate-drain, and other capacitanceinherent in the transistors coupled to the first summer 790. The seconddevice capacitance 793 is a lumped element representation of thegate-source, gate-drain, and other capacitance inherent in thetransistors coupled to the second summer 791. The first devicecapacitance 790 must be the same as the second device capacitance 791for the clock rising edge 680 and the adjusted clock rising edge 681 tohave the same slope and remain aligned.

[0075] At steady state the clock signal 524 and the adjusted clocksignal 523 are equal to the voltage supply 701.

[0076] Referring to FIG. 7, the input clock 460 is inverted and appliedto input 401 and the first gate 711, the second gate 721, the third gate753, the fourth gate 761, and the fifth gate 781. The rising edge 471 ofthe input clock 460 lowers the reverse gate to source bias on the firsttransistor 710 and the third transistor 750. The first transistor 710begins to conduct current from the first source 713 to the first drain712. The drain current increases the voltage at the first summer 790 andacross the first device capacitance 792. The voltage at the first summer790 is output as clock signal 524. The rate of change or slope in theclock signal 524 is proportional to the first device capacitance 792.

[0077] The third transistor 750, simultaneous with the first transistor710, begins to conduct current from the third source 752 to the thirddrain 751. The rising voltage at second summer 791 is output as theadjusted clock rising edge 681. The slope in the adjusted clock risingedge 681 is proportional to the second device capacitance 793.

[0078] When the falling edge 474 of the input clock 460 is applied tothe input 401, the first transistor 710 and the third transistor 750 arereverse biased and stop conducting. The falling edge 474 simultaneouslycauses the second transistor 720 to conduct. The voltage at the firstsummer 790 and across first device capacitance 792 decreases and isoutput as the clock falling edge 682 of the clock signal 524. The firstdevice capacitance 792 is unchanged. The magnitude of the slope of theclock falling edge 682 will remain the same as it was for the clockrising edge 680.

[0079] The falling edge 474 also causes the fourth transistor 760, andthe fifth transistor 779 to conduct. The second device capacitance 793is unchanged.

[0080] The fourth transistor 760 and the fifth transistor 779 are bothdecreasing the voltage at the second summer 791 which is also across thesecond device capacitance 793 The rate of voltage change is directlyproportional to current flow. Therefore, the additional current from thefifth transistor 779 will increase the slope of the adjusted clockfalling edge 683. The increased slope of adjusted clock falling edge 683pulls down the voltage at the second summer 791 faster than the secondtransistor 720.

[0081] The device capacitance 792 must also be equal to the seconddevice capacitance 793 to keep the clock falling edge 682 and theadjusted clock falling edge 683 aligned. The first device capacitance792 and the second device capacitance 793 must also be equal to keep theclock rising edge 680 and the adjusted clock rising edge 681 aligned. Inone embodiment the first device capacitance 792 and the second devicecapacitance 793 are matched by placing transistors with substantiallyidentical characteristics in corresponding positions in the othercircuit. For example, the following transistor pairs should be selectedto have the same characteristics, the first transistor 710 and the thirdtransistor 750, the second transistor 720 and the fourth transistor 760,the fifth transistor 779 and the seventh transistor 740, and the sixthtransistor 770 and the eighth transistor 730.

[0082] The slope of the adjusted clock falling edge 683 is controlled byadding or removing transistors with their gate coupled to the input 401and conducting in parallel with the fifth transistor 779. If the fifthgate 781 is coupled to the ground 702, the adjusted clock falling edge683 will be identical to the clock falling edge 682.

[0083] If an additional transistors is added, it must be mirrored by anidentical transistor to keep the first device capacitance 792 equal tothe second device capacitance 793. For example, if two additionaltransistors have their sources, gates and drains coupled identically tothe fifth transistor 779, two identical transistors with their sources,drains, and gates coupled like the seventh transistor 740.

[0084]FIG. 8 illustrates a method for generating a multi-phase clockaccording to the present invention. In step 810, an external clocksignal is received. In step 820, the clock signal is separated intorising edges and falling edges. In step 830, The rising edges arecoupled to a first and a second summer. In step 840, the slope of afalling edge is adjusted to create an adjusted falling edge. In step850, the adjusted falling edge and a rising edge are summed to output anadjusted clock signal. In step 860, a falling edge and a rising edge aresummed to output a clock signal.

[0085]FIG. 9 illustrates details of method step 840. In step 905, a timedifference between an adjusted falling edge and a falling edge isselected. The time difference is selectable from zero to a desiredvalue. In step 910, The slope of a falling edge is adjusted to create anadjusted falling edge. A falling edge and the adjusted falling edge aremisaligned by the calculated time difference.

CONCLUSION

[0086] Example embodiments of the methods, circuits, and components ofthe present invention have been described herein. As noted elsewhere,these example embodiments have been described for illustrative purposesonly, and are not limiting. Other embodiments are possible and arecovered by the invention. Such embodiments will be apparent to personsskilled in the relevant art(s) based on the teachings contained herein.Thus, the breadth and scope of the present invention should not belimited by any of the above-described exemplary embodiments, but shouldbe defined only in accordance with the following claims and theirequivalents.

What is claimed is:
 1. An alignment circuit comprising: an input; adiscriminator coupled to said input, and having a rise output and a falloutput; a first summer coupled to said rise output and said fall output;a rate adjust coupled between said fall output and a second summer; anoutput coupled to said first summer; and an adjusted output coupled tosaid second summer.
 2. The alignment circuit of claim 1, wherein saiddiscriminator outputs a rising pulse edge from a signal at said input atsaid rise output and couples a falling pulse edge from said signal atsaid fall output.
 3. The alignment circuit of claim 2, wherein said rateadjust modifies a slope of said falling pulse edge and outputs anadjusted falling pulse edge to said second summer.
 4. The alignmentcircuit of claim 3, wherein said output is a sum of said rising pulseedge and said falling pulse edge.
 5. The alignment circuit of claim 3,wherein said adjusted output is a sum of said adjusted falling pulseedge and said rising pulse edge.
 6. The alignment circuit of claim 2,further comprising: a second rate adjust coupled between said riseoutput and said first summer, wherein said second rate adjust modifiesthe slope of said rising pulse edge and outputs an adjusted rising edge;said first summer combines said fall output and said adjusted risingedge.
 7. A method of adjusting pulse edges comprising the steps of: (1)receiving a clock signal; (2) differentiating between a rising edge anda falling edge in said clock signal; (3) coupling said rising edge andsaid falling edge to a first summer and a second summer; (4) adjusting aslope of said falling edge to create an adjusted falling edge; (5)summing said adjusted falling edge and said rising edge to output anadjusted clock signal; and (6) summing said falling edge and said risingedge to output a clock signal.
 8. The method of claim 7, wherein step(4) comprises: (4) adjusting the slope of said rising edge to create anadjusted rising edge.
 9. The method of claim 7, wherein step (5)comprises: (5) summing said adjusted rising edge and said falling edgeto output an adjusted rising edge.
 10. The method of claim 7, whereinsaid adjusting step comprises: (6) selecting a time difference betweenan adjusted falling edge and said falling edge, wherein said timedifference is selectable from zero to a desired value; and (7) adjustingthe slope of said falling edge to create said adjusted falling edge,wherein said falling edge and said adjusted falling edges are misalignedby said time difference.